1. Field of the Invention
As processors have gotten cheaper, more and more digital data processing systems have appeared in which several processors operate as coprocessors. A coprocessor is a processor which cooperates with another processor to process data. Classic examples of coprocessors are floating-point units for performing floating point arithmetic and I/O processors for handling the flow of data between peripheral devices such as terminals and the system memory. The relationship between two coprocessors lies along a continuum whose ends are described by the notions tightly coupled and loosely coupled. One coprocessor is tightly coupled to another when there is a high degree of direct interaction between the coprocessors. For example, floating point units are typically tightly coupled. The processor served by the floating point unit provides the operands to the floating point unit, indicates the operation to be performed, and receives the results directly from the floating point unit. The results typically not only include the result value, but also signals indicating the status of the floating point operation. I/O processors, on the other hand, are typically loosely coupled. Communication with the processor they serve is generally through the system memory. When the processor requires the assistance of the I/O processor to output data, the processor places the output data and a description of what the I/O processor is to do with it in memory at a location known to the I/O processor and then indicates to the I/O processor that the data is in memory. The I/O processor thereupon responds to the indication by retrieving the data from memory and outputting it to the desired peripheral device. When it is finished, it puts a record of the status of the operation in memory at a location known to the processor and indicates to the processor that it has finished the memory operation. The processor then responds to the indication by reading the data at the location to determine the status of the output operation.
2. Description of the Prior Art
Coprocessors necessarily share resources with other processors. One consequence of this is that the time required for a coprocessor to execute an instruction which involves a shared resource is unpredictable. For example, the time it takes to perform a memory read or write operation depends on whether the coprocessor has immediate access to the bus and on whether the memory is busy. The unpredictability of execution time is particularly problematic in processors which increase execution speed by pipelining instruction execution.
Pipelining works as follows: The execution of any instruction has a number of phases. For example, with a MOVE instruction which moves data from one register to another, it is typically necessary to fetch the MOVE instruction, to decode it to determine that it is a MOVE instruction and to determine which register is the source of the data being moved and which the destination, and to actually execute the instruction by moving the data from the source register to the destination register. When instruction execution is pipelined, the phases of execution are performed in parallel on different instructions. For instance, if a pipelined processor is executing three instructions in the order n1, n2, and n3, it may be simultaneously performing the execution phase on n1, the decode phase on n2, and the fetch phase on n3.
Pipelining works well as long as all of the instructions have the same number of phases, or at least have a fixed number of cycles of execution. The difficulty comes when a first instruction which does not have a fixed number of cycles of execution is followed by a second instruction which is dependent on the results of the execution of the first instruction. In that case, the execution of the second instruction must be halted until execution of the first instruction is complete, and while execution of the second instruction is halted, the entire pipeline is halted. Such halting of a pipeline to await the conclusion of execution of an instruction is termed a pipeline exception or stall in the art. Dealing with pipeline stalls is an important problem in the design of pipelined processors. It is an object of the invention described in the present application to provide an instruction which prevents pipeline stalls in certain situations.